1. Field of the Invention
This invention relates to the clocked static memory and more specifically to a clocked static memory with logic circuit for creating a memory status signal to indicate the availability of valid data output.
2. Description of the Prior Art
Conventional static memories have been produced on semiconductor substrates by using semiconductor technology, especially MOS (metal oxide semiconductor) technology. A plurality of memory cells are arranged on the substrate in a matrix with each of the memory cells connected to a word select line and a pair of bit lines. Each memory cell generally comprises a latch of flip-flop circuit formed by MOS transistors.
The word select lines are connected to and selected by a row address decoder network whereas each pair of bit lines is selected responsive to a column address decoder.
Various static memories include a latch or dynamic presense amplifier connected between the pair of bit lines to detect a signal from the selected memory cell in the column. The bit line signal is transferred to data lines through control gates and finally amplified in a sense amplifier commonly connected to the data lines.
Recently, a MOS static memory was introduced in which a reference row was created with the resistance and capacitive loading equal to that of the row or word select lines. The reference row is a part of the memory matrix and comprised of a reference line loaded with a pair of transistors in each column which represent the cell loading. A buffer amplifier is connected to the end of the reference line. A reference row driver is clocked by the same clock signal as the decoder and the output of the reference row driver is supplied to the reference line.
The buffered output is also connected to a delay element thereby providing a properly delayed memory status output signal. For that purpose, it is required that there be a proper choice and design of delay element. The memory status output signal is used as a clock signal to the following circuits instead of the conventional clock signal thereby enabling faster acquisition of accessed data and improving the system performance. Because of parameter variations of the elements which are commonly encountered in actual fabrications of MOS memories, difficulties are encountered in realizing properly timed memory status output signals. Such a circuit is illustrated and described in an article of the IEEE Journal of Solid-State Circuits, Volume SC-11, No. 5, October 1976, entitled "Two 4K Static RAM's."